? semiconductor components industries, llc, 2013 july, 2013 ? rev. 1 1 publication order number: CAT5136/d CAT5136, cat5137, cat5138 digital potentiometer (pot) with 128 taps and i 2 c interface description CAT5136, cat5137, and cat5138 are a family of digital pots operating like mechanical potentiometers in various configurations. the tap points between the 127 equal resistive elements are connected to the wiper output via cmos switches. the switches are controlled by a 7-bit wiper control register (wcr) via the i 2 c serial bus. CAT5136 is configured as a variable resistor. cat5137 and cat5138 are resistive voltage dividers, with one terminal of the potentiometer connected to gnd. ca t5137 and cat5138 have different device ids, which makes it possible to use both on the same i 2 c bus. upon power-up, the wcr is set to mid-scale (1000000). features ? single linear digital potentiometer with 128 taps ? end-to-end resistance of 10 k , 50 k and 100 k ? i 2 c interface ? wiper goes to midscale at power-up ? digital supply range (v dd ): 2.7 v to 5.5 v ? low standby current ? industrial t emperature range: ? 40 ? c to +85 ? c ? 6-pin sc ? 70 package ? these devices are pb-free, halogen free/bfr free and are rohs compliant typical applications ? lcd screen adjustment ? volume control ? mechanical potentiometer replacement ? gain adjustment ? line impedance matching ? vcom setting adjustments http://onsemi.com sc ? 70 sd suffix case 419ad pin connections (top views) 1 3 4 5 vdd gnd scl sda rl rw 2 6 CAT5136 1 3 4 5 vdd gnd scl sda rh rw 2 6 cat5137 cat5138 (for low pin count devices) see detailed pin function descriptions on page 2. see detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. ordering information
CAT5136, cat5137, cat5138 http://onsemi.com 2 figure 1. block diagram sda scl rw rh vdd gnd (cat5137, cat5138) power on midscale i 2 c interface and control sda scl rw rl vdd gnd (CAT5136) power on midscale i 2 c interface and control table 1. pin function description pin no. pin name description CAT5136 cat5137/cat5138 1 1 vdd digital supply voltage (2.7 v to 5.5 v) 2 2 gnd ground 3 3 scl serial bus clock input for the i 2 c serial bus. this clock is used to clock all data transfers into and out of the CAT5136 ? 8 4 4 sda serial data input/output ? bidirectional serial data pin used to transfer data into and out of the CAT5136 ? 8. this is an open-drain i/o and can be wire or?d with other open-drain (or open collector) i/os. 5 5 rw wiper terminal for the potentiometer 6 ? rl low reference terminal for the potentiometer ? 6 rh high reference terminal for the potentiometer table 2. absolute maximum ratings parameter symbol range unit temperature under bias ? 55 to +125 ? c storage temperature range t stg ? 65 to 150 ? c voltage on any sda, scl, a0 & a1 pins with respect to ground (note 1) ? 0.3 to v dd + 0.3 v voltage on rh, rl & rw pins with respect to ground ? 0.3 to v dd + 0.3 v v dd with respect to ground ? 0.3 to +6 v wiper current (10 sec) ? 6 ma lead soldering temperature (10 sec) +300 ? c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. latch-up protection is provided for stresses up to 100 ma on address and data pins from ? 0.3 v to v dd +0.3 v. table 3. recommended operation conditions parameter symbol value unit digital supply voltage v dd +2.7 to +5.5 v operating temperature range ? 40 to +85 ? c
CAT5136, cat5137, cat5138 http://onsemi.com 3 table 4. potentiometers characteristics (over recommended operating conditions unless otherwise stated.) parameter symbol test conditions limits units min typ max potentiometer resistance (10 k ) r pot 10 k potentiometer resistance (50 k ) r pot 50 k potentiometer resistance (100 k ) r pot 100 k potentiometer resistance tolerance r tol ? 20 % power rating 25 ? c 50 mw wiper current i w ? 3 ma wiper resistance r w v dd = 3.3 v 85 200 voltage on r w , r h or r l v term gnd = 0 v; v dd = 2.7 v to +5.5 v gnd v dd v resolution res 0.78 % integral non-linearity (note 3) inl v w(n)(actual) ? v w(n)(expected) (notes 6, 7) ? 1 lsb (note 5) differential non-linearity (note 4) dnl v w(n+1) ? [v w(n) +lsb] (notes 6, 7) 1 lsb (note 5) resistor integral non-linearity r inl r n ? n*lsb (notes 6, 8) ? 2 lsb (note 5) resistor differential non-linearity r dnl r n ? [r n ? 1 + lsb] (notes 6, 8) ? 1 lsb (note 5) temperature coefficient of r pot t crpot (note 2) ? 300 ppm/ ? c ratiometric temperature coefficient t cratio (note 2) 30 ppm/ ? c potentiometer capacitances c h /c l /c w (note 2) 10/10/25 pf frequency response fc r pot 0.4 mhz 2. this parameter is tested initially and after a design or process change that affects the parameter. 3. integral non-linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 4. differential non-linearity is utilized to determine the actual change in voltage between two successive tap positions when us ed as a potentiometer. 5. lsb = (r hm ? r lm )/127; where r hm and r lm are the highest and lowest measured values on the wiper terminal. 6. n = 1, 2, ..., 127 7. v dd @ r h ; v w measured @ r w with no load. 8. rw and r l in the range of 0 v and v dd . table 5. d.c. electrical characteristics (over recommended operating conditions unless otherwise stated.) parameter symbol test conditions min max units power supply current (write/read) i dd f scl = 400 khz, sda open, v dd = 5.5 v, input = gnd 200 a standby current i sb(vdd) v in = gnd or v dd , sda = v dd 0.5 a input leakage current i li v in = gnd to v dd ? 1 1 a output leakage current i lo v out = gnd to v dd ? 1 1 a input low voltage v il ? 0.3 v dd x 0.3 v input high voltage v ih v dd x 0.7 v dd + 0.3 v output low voltage (v dd = 3.0 v) v ol i ol = 3 ma 0.4 v
CAT5136, cat5137, cat5138 http://onsemi.com 4 table 6. a.c. characteristics parameter (see figure 6) symbol min typ max units clock frequency f scl 400 khz noise suppression time constant at scl & sda inputs t i (note 9) 50 ns scl low to sda data out and ack out t aa 1 s time the bus must be free before a new transmission can start t buf (note 9) 1.2 s start condition hold time t hd:sta 0.6 s clock low period t low 1.2 s clock high period t high 0.6 s start condition setup time (for a repeated start condition) t su:sta 0.6 s data in setup time t su:dat 100 ns data in hold time t hd:dat 0 s sda and scl rise time t r (note 9) 0.3 s sda and scl fall time t f (note 9) 300 ns stop conditions setup time t su:sto 0.6 s data out hold time t dh 100 ns 9. this parameter is tested initially and after a design or process change that affects the parameter. table 7. capacitance (t a = 25 ? c, f = 1.0 mhz, v dd = 5.0 v) parameter symbol test conditions min typ max unit input/output capacitance (sda, sdc) c i/o v i/o = 0 v (note 10) 10 pf 10. this parameter is tested initially and after a design or process change that affects the parameter. table 8. power-up timing (notes 11, 12) symbol parameter min max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms 11. this parameter is tested initially and after a design or process change that affects the parameter. 12. t pur and t puw are the delays required from the time v dd is stable until the specified operation can be initiated. table 9. wiper timing symbol parameter min max units t wrpo wiper response time after power supply stable 5 10 s t wrl wiper response time after instruction issued 5 10 s
CAT5136, cat5137, cat5138 http://onsemi.com 5 typical performance characteristics figure 2. resistance between r w and r l figure 3. power supply current tap position v cc (v) 112 96 80 64 48 32 16 0 0 10 20 30 40 50 60 6 5 4 3 2 0 10 20 40 50 60 80 90 figure 4. integral non ? linearity figure 5. differential non ? linearity tap position tap position 112 96 80 64 48 32 16 0 ? 1.0 ? 0.8 ? 0.6 ? 0.2 0 0.4 0.8 1.0 112 96 80 64 48 32 16 0 ? 1.0 ? 0.8 ? 0.4 ? 0.2 0 0.2 0.6 1.0 r wl (k ) i cc ( a) inl (lsb) dnl (lsb) 128 128 ? 0.4 0.2 0.6 128 ? 0.6 0.4 0.8 30 70 v cc = 2.7 v v cc = 5.5 v rheostat configuration t a = +25 ? c, r pot = 50 k v cc = 2.7 v v cc = 5.5 v potentiometer configuration t a = +25 ? c, r pot = 10 k v cc = 2.7 v v cc = 5.5 v potentiometer configuration ? 40 ? c 25 ? c 90 ? c 125 ? c scl sda in sda out figure 6. bus timing t su:sta t hd:sta t hd:dat t aa t f t low t high t low t r t su:dat t dh t su:sto t buf
CAT5136, cat5137, cat5138 http://onsemi.com 6 serial bus protocol the following defines the features of the i 2 c bus protocol: 1. data transfer may be initiated only when the bus is not busy. 2. during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock is high will be interpreted as a start or stop condition. the device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the cat513x will be considered a slave device in all applications. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat513x monitors the sda and scl lines and will not respond until this condition is met (see figure 7). stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition (see figure 7). acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data (see figure 8). the cat513x responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. when the cat513x is in a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat513x will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. start condition sda stop condition scl figure 7. start/stop condition 189 start scl from master bus release delay (transmitter) bus release delay (receiver) data output from transmitter data output from receiver figure 8. acknowledge condition ack delay ( ? t aa ) ack setup ( ? t su:dat )
CAT5136, cat5137, cat5138 http://onsemi.com 7 device description slave address instruction byte description the first byte sent to the cat513x from the master processor is called the slave address byte. the most significant seven bits of the slave address are a device type identifier. for CAT5136 and cat5137 these bits are fixed at 0101110. for cat5138, they are 01 11110. this allows both cat5137 and cat5138, which are functionally identical, to reside on the same bus (refer to table 10). only the device with slave address matching the input byte will be accessed by the master. the last bit is the read/write bit and determines the function to be performed. if it is a ?1? a read command is initiated and if it is a ?0? a write is initiated. after the master sends a start condition and the slave address byte, the cat513x monitors the bus and responds with an acknowledge when its address matches the transmitted slave address. table 10. byte 1 slave address and instruction byte device device type identifier read/write id6 id5 id4 id3 id2 id1 id0 CAT5136 0 1 0 1 1 1 0 r/w cat5137 0 1 0 1 1 1 0 r/w cat5138 0 1 1 1 1 1 0 r/w (msb) (lsb) wiper control register (wcr) description the cat513x contains a 7-bit volatile wiper control register which is decoded to select one of the 128 switches along its resistor array. the wiper control register loses its contents when the cat513x is powered-down. at power-up, the register is loaded with the midscale value 40h. the contents of the wcr may be read or changed directly by the host using a read/write command on the i 2 c bus (see table 1 to access wcr). since the cat513x will only make use of the 7 lsb bits, the first data bit, or msb, is ignored on write instructions and will always come back as a ?0? on read commands. a write operation (see table 11) requires a start condition, followed by a valid slave address byte, a valid address byte 00h, a data byte and a stop condition. after each of the three bytes, the cat513x responds with an acknowledge. after th e third byte, the data is w ritten to the wiper control register, and the wiper changes position accordingly. a read operation (see table 12) requires a start condition, followed by a valid slave address byte for write, a valid address byte 00h, a second start and a second slave address byte for read. after each of the three bytes, the cat513x responds with an acknowledge and then the device transmits the data byte. the master terminates the read operation by issuing a stop condition following the last bit of data byte. table 11. write operation CAT5136 and cat5137 start 1st byte ack 2nd byte ack 3rd byte ack stop slave address wb address byte data byte in s 0 1 0 1 1 1 0 0 a 0 0 0 0 0 0 0 0 a x d6 d5 d4 d3 d2 d1 d0 a p cat5138 start 1st byte ack 2nd byte ack 3rd byte ack stop slave address wb address byte data byte in s 0 1 1 1 1 1 0 0 a 0 0 0 0 0 0 0 0 a x d6 d5 d4 d3 d2 d1 d0 a p
CAT5136, cat5137, cat5138 http://onsemi.com 8 table 12. read operation CAT5136 and cat5137 start 1st byte ack 2nd byte ack start 3rd byte ack 4th byte noack stop slave address wb address byte slave address r output data byte s 0 1 0 1 1 1 0 0 a 0 0 0 0 0 0 0 0 a s 0 1 0 1 1 1 0 1 a 0 d6 d5 d4 d3 d2 d1 d0 na p cat5138 start 1st byte ack 2nd byte ack start 3rd byte ack 4th byte noack stop slave address wb address byte slave address r output data byte s 0 1 1 1 1 1 0 0 a 0 0 0 0 0 0 0 0 a s 0 1 1 1 1 1 0 1 a 0 d6 d5 d4 d3 d2 d1 d0 na p potentiometer operation CAT5136, cat5137, cat5138 are a family of a 128-position, digital controlled potentiometers. when v dd is applied, the device automatically turns on at the mid-point wiper location (64). at power-down, it is recommended to turn-off first the signals on rh, rw and rl, followed by vdd, in order to avoid unexpected transitions of the wiper and uncontrolled current overload of the potentiometer. the end-to-end nominal resistance of the potentiometer has 128 contact points linearly distributed across the total resistor. each of these contact points is addressed by the 7 bit wiper register which is decoded to select one of these 128 contact points. each contact point generates a linear resistive value between the 0 position and the 127 position. these values can be determined by dividing the end-to-end value of the potentiometer by 127. in the case of the 50 k potentiometer ~390 is the resistance between each wiper position. however in addition to the ~390 for each resistive segment of the potentiometer, a wiper resistance offset must be considered. table 13 shows the effect of this value and how it would appear on the wiper terminal. table 13. potentiometer resistance and wiper resistance offset effects position typical rw to rl resistance for 50 k digital potentiometer 00 70 or 0 + 70 01 460 or 390 + 70 63 24,870 or 24,800 + 70 127 50,070 or 50,000 + 70
CAT5136, cat5137, cat5138 http://onsemi.com 9 table 14. ordering information device order number specific device marking package type temperature range resistance (k ) lead finish shipping ? CAT5136sdi ? 50gt3 p64 sc ? 70 ? 6 i = industrial ( ? 40 ? c to +85 ? c) 50 nipdau 3,000 / tape & reel cat5137sdi ? 10gt3 (note 14) p72 sc ? 70 ? 6 i = industrial ( ? 40 ? c to +85 ? c) 10 nipdau 3,000 / tape & reel cat5137sdi ? 00gt3 p75 sc ? 70 ? 6 i = industrial ( ? 40 ? c to +85 ? c) 100 nipdau 3,000 / tape & reel cat5138sdi ? 10gt3 p82 sc ? 70 ? 6 i = industrial ( ? 40 ? c to +85 ? c) 10 nipdau 3,000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. 13. for detailed information and a breakdown of device nomenclature and numbering systems, please see the on semiconductor device nomenclature document, tnd310/d, available at www.onsemi.com 14. contact factory for availability.
CAT5136, cat5137, cat5138 http://onsemi.com 10 package dimensions sc ? 88 (sc ? 70 6 lead), 1.25x2 case 419ad issue a e1 d a l l1 l2 ee b a1 a2 c top view side view end view 1 1 notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-203. e symbol min nom max a a1 b c d e e1 e l 0o 8o l2 0.00 0.15 0.10 0.26 1.80 1.80 1.15 0.65 bsc 0.15 bsc 1.10 0.10 0.30 0.18 0.46 2.20 2.40 1.35 l1 0.80 1 4o 10o a2 0.80 1.00 0.42 ref 0.36 2.00 2.10 1.25 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 CAT5136/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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